SemiAnalysis tore down a shipped Intel Panther Lake part, identified in the piece as a Core Ultra 7 365. The article's judgment is that backside power delivery has a first commercial implementation, that Intel's first gate-all-around transistors have shipped, and that the advanced package uses Foveros-S. They treat this as the point where Intel's manufacturing plans became shipped silicon, and they say they opened the chip to see how far that comeback has gone.

The compute logic is Intel 18A. The teardown starts from four-sheet RibbonFETs, Intel's marketing name for its gate-all-around transistors. The piece's measurements put Panther Lake's 18A compute logic and the TSMC N3E GPU logic at similar logic density. 18A does not lead TSMC N3P or N2, or Samsung SF2, in peak density. The CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E.

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Letterpress cross-section of a chip, with copper power rising from below the transistors.
Thin signal lines sit above, and thicker supply lines arrive from the back. It stands for backside power in the teardown, and it is not a micrograph., AI-generated illustration, not a news photograph

The package stacks one compute tile, one GPU tile, and one I/O tile on a passive base tile, assembled with Foveros-S. Both compute-tile variants use Intel 18A. The Xe3 GPU comes in two options: a 4-core GT1 tile on Intel 3, and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6.

Intel's name for backside power is PowerVia. In a conventional chip, power and signal share the frontside metal, and the power rails take routing space next to the transistors. PowerVia moves the main power network behind the transistors. Dedicated backside metals reach nano-TSVs, which connect to the local source and drain contacts. The frontside signal stack runs from M0 to M14. The backside power stack runs from BM0 to BM5. M0 and BM0 sit closest to the transistors.

Intel patterns the nano-TSVs from the front after the contacts are formed. A narrow via runs from the side of the contact down into the silicon. After the frontside metals are finished, the wafer is bonded to a carrier, flipped, and the original substrate is removed until the buried via tips are exposed. The backside metals are then built on those exposed vias. The carrier stays above the frontside interconnects. It holds the wafer during thinning, and it remains part of the finished chip's thermal path. In one cross-section, the tapered connection from the contact level to BM0 spans roughly 150 nanometers.

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PowerVia's lateral landing still takes area inside the standard cell, so it recovers less cell area than a direct backside contact. The piece uses Samsung SF2 as a comparison: an incumbent gate-all-around foundry node that does not have backside power.

The public portion is about a client Panther Lake processor, not an AI accelerator. The density comparison, the metal-layer counts, and the roughly 150 nanometers are SemiAnalysis's teardown figures, not an Intel specification sheet. The saved text breaks off during the backside-metal etch, and later measurements are not in this piece.

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要点

  • Shipped Panther Lake parts carry commercial backside power and Intel's first gate-all-around transistors.
  • 18A compute logic is similar in density to TSMC N3E GPU logic, and it does not lead N3P, N2, or Samsung SF2 at peak density.
  • The high-end GPU is still TSMC N3E, and the CPU cores are incremental.
  • PowerVia routes supply from the backside; one cross-section spans about 150 nanometers from the contact to BM0.